We write, we don’t plagiarise! Every answer is different no matter how many orders we get for the same assignment. Your answer will be 100% plagiarism-free, custom written, unique and different from every other student.
I agree to receive phone calls from you at night in case of emergency
Please share your assignment brief and supporting material (if any) via email here at: email@example.com after completing this order process.
No Plagiarism Guarantee - 100% Custom Written
19: Electronic Devices and Circuits
Assignment title Digital electronic devices and circuits
Learning aim(s) (For NQF only)
B: Explore the safe operation and applications of digital logic devices and circuits that form the building blocks of commercial circuits.
You have been asked to carry out a range of theoretical and practical investigations and evaluations into digital devices and circuits. To do this: Your teacher will provide you with information about two types of circuit that you need to investigate:
(a) One combinational (combinatorial) logic circuit; and
(b) Two sequential (clocked) logic circuits You must provide evidence that you have consistently worked safely in accordance with relevant risk assessments. You shall produce a report that includes information about the operation of the circuits, including comparisons between theoretical values, simulated values, and those measured practically. You will investigate the following:
a) a combinational logic circuit;
b) a 3-bit shift register circuit; and
c) a 3-bit asynchronous (ripple) counter circuit. To do this you will need to work systematically, following the guide below:
Task 1 a ) Combinational logic circuit A chemical process is controlled by a logic circuit. The circuit uses three sensors A, B and C, and switches an alarm on, by causing the circuit’s output Q to become high/ON (= 1), when certain conditions are reached. Input Description of function Input logic state A Flow rate ≥ 5 litres/second 1 Flow rate < 5 litres/second 0 B Temperature ≥ 30oC 1 Temperature < 30oC 0 C Pressure ≥ 1 atmosphere 1 Pressure < 1 atmosphere 0 You should: Draw the truth table for the logic circuit if the conditions for the alarm Q=1 are: Flow rate < 5 litre/second OR Temperature ≥ 30oC AND Pressure ≥ 1 atmosphere OR Flow rate ≥ 5 litre/second and Temperature ≥ 30oC Use this information to write a Boolean expression for the truth table using AND, OR and NOT statements e.g. “Q=A AND (B OR C)”, and using Boolean algebra e.g. “A(B+C)” to demonstrate your understanding .
You then need to:
(i) Construct a schematic diagram and simulate the operation of the logic circuit using standard 2-input logic gates connected to each other;
(ii) Minimize the logic circuit using a Karnaugh Map, and then construct a schematic diagram of the minimized circuit,
(iii) verify that the truth table for the minimized circuit is identical to that of the original circuit, and (iv) simulate the operation of the minimized logic circuit, using standard logic gates.
(v) Use De Morgan’s Theorems to convert the minimized circuit to use only NAND gates.
(vi) Build a prototype of your final circuit (comprising NAND gates) and verify by testing, that it meets the conditions in the truth table. Compare the results from theory, simulation and measurement.
Task 1 b1) 3-bit shift register You should: Identify the ‘pin-out’ of a 74HC74 dual D-type flip-flop integrated circuit with positive-edge trigger [or the pin-out of an equivalent integrated circuit that you have available]. Note: ‘flip-flop’ means bi-stable. Construct a schematic circuit diagram of a 3-bit shift register using D-type flipflops in your ECAD package. The 74HC74 in the schematic below has PReset held HIGH (+5V, logic 1) and CLR pin held low (logic 0) to allow changes at the D pin to clock through to the output Q. The schematic diagram that you produce should be for the integrated circuit that you have available, and which you will use to build a prototype circuit in the laboratory/classroom.
(i) Use the schematic to simulate the behavior of the circuit by setting data values at the D1 input and clocking them through.
(ii) Build a prototype of the same circuit (as drawn in your simulation) and demonstrate that it works as expected. Then compare the results from theory (based on what you have been taught), simulation and observations you made on the actual built prototype circuit.
(iii) State what practical improvements would you make to the circuit, if any.
(iv) The circuit above shifts data from left to right. Draw a schematic diagram of a logic circuit to show how individual logic gates can be connected together and used to enable data to be shifted from right to left. See references on logic circuits given to you by your teacher.
(v) Simulate the circuit designed in the previous step above, to demonstrate how the circuit can shift data from left to right or right to left, depending on a digital input signal (which can be 1 or 0).
Task 1 b2) 3-bit asynchronous (ripple) counter You should:
Identify the pin-out of a 4027B dual JK flip-flop with positive-edge trigger [or specify an equivalent that you have available]
Construct in your ECAD package the schematic circuit, shown below, of a 3-bit asynchronous counter using JK flip-flops. The 4027B in the schematic has certain pins held low (logic 0) or high (logic 1) to allow changes to clock through to the output Q. Explain why those inputs are held low or high.
(i) Use the schematic to simulate the behavior of the circuit by using the switch S1 as a manual clock.
(ii) Build a prototype of the same circuit and verify that it works as expected, and then compare the results from theory (what you know and expect), simulation (using ECAD e.g. logic.ly/demo), and measurements.
(iii) What practical improvements could you make to the circuit?
(iv) Draw a schematic diagram to show how individual logic gates can be added to the up-counter in the diagram to convert it into an up/down counter - do research as appropriate.
(v) Simulate, using ECAD, the circuit drawn in the previous step, to demonstrate how the circuit can be used as an up or down counter.